Gate arrays are used extensively to fabricate integrated circuits which perform customer specialized functions. The semiconductor devices of the gate arrays are designed into base patterns and fabricated into wafers for customer specific functional interconnection during metallization. Consequently, the integrated circuit semiconductor devices can be interconnected to perform the logic functions desired by a customer in the relatively short time needed to form the metallization patterns.
The metallization process by which the pre-existing transistors and other active devices in the base set are interconnected to form functional configurations typically uses one or more metallization layers, a pattern of contacts that connect from the metallization layers to the semiconductor regions, and vias to interconnect the successive metallization patterns.
Higher density and more reliable devices, with lower levels of power consumption, are desirable. However, integrated circuit design rules impose a number of constraints on the interconnection of the transistors, hampering design efforts towards higher density. For example, a gate array design must satisfy minimum polysilicon width dimensions, minimum spacing between polysilicon conductors, minimum metal width dimensions, minimum spacing between metal conductors, minimum dimensions for contacts, minimum dimensions for vias, and constraints as to vertical placement on the various consecutive layers. Gate array cell architecture designers set a track pitch of routing tracks, connecting gate cells in an array, at a constant value that satisfies the largest of all of the minimum spacings. These limitations may be understood with respect to FIGS. 1 and 2.
FIG. 1 is a schematic depiction of a cell of a prior art gate array, for purposes of explaining some limitations of the prior art gate arrays. This cell, which is replicated numerous times in a tile pattern on a chip, h a number of polysilicon layer patterns 10 fur transistor gate electrodes. A P channel diffusion area 12 forms the P channel device and an N channel diffusion area 14 forms the N channel device. A P channel well tap is provided at area 16, and an N channel well tap is provided at area 18.
The lower half of the gate cell in FIG. 1 has its components interconnected to form a device within the gate cell, such as a NAND gate, AND gate, NOR gate and OR gate. The interconnecting of the components of the gate cell to form the device is performed in metallization layers. The first metallization layer forms the primary interconnections of the components of the gate cell that form the devices. For reasons described below, it is often necessary, however, to use a second metallization layer to complete the interconnection of the devices within the gate cell.
In FIG. 1, the components in the lower half of the gate cell are connected together by the first metal in the first metallization layer to form a NAND gate with input ports A and B and an output port Z. These interconnections are depicted as dotted regions in FIG. 1. The VSS and VDD power buses (20, 22) for the devices extend vertically across the gate cells, as indicated in FIG. 1. These buses 20, 22 limit the amount of interconnection that is possible within the gate cells to the area located horizontally between the two buses 20, 22, at least within the first metallization layer. Due to the limited amount of interconnectivity caused by the location of the buses in the first metallization layer, the second metallization layer is typically required to form interconnections within the gate cell to form the devices. The use of second metal in the second metallization layer to form the devices creates a "porosity" problem in the conventional architecture.
In FIG. 2, cells 24 are arranged in cell placement columns 26, separated by routing columns 28. The horizontal routing tracks through a cell 24 are provided in the second metallization layer direction, and are also seen in FIG. 1 with reference numeral 30. These routing tracks (hereinafter referred to as m2 routing tracks) 30 are used to provide horizontal connections between gate cells 24. The vertical routing tracks 32, (also shown in FIG. 1 and hereinafter referred to as m1 routing tracks) extend in a vertical direction through the gate cells 24 and in the routing channels 28. These ml tracks 32 are found in the first metallization layer.
The problem caused by using the second metallization layer to form the devices within the gate cell becomes apparent with reference made to FIGS. 1 and 2. In FIG. 1, there are only three m2 tracks 30 that pass through the device. When the second metal is used to interconnect the components of the gate cell to form a device, the m2 routing tracks 30 running horizontally will be effectively not useable for connecting the device in the gate cell to the device in another gate cell. In other words, the m2 routing track 30 will be blocked. With only three possible m2 routing tracks 30 running through the device, and given the limited amount of interconnectivity available between the power buses 20, 22, it is likely that the three m2 routing tracks 30 will be blocked by the second metal required to complete formation of the device. Since there are very few or no "route throughs" in such cells, these cells are considered to have a "low porosity".
The low porosity of the cells causes many detours to be taken when routing devices together, as depicted in the example of FIG. 2. In this case, connecting the device of gate cell 24A to the device of gate cell 24B requires a tortuous path to a gate cell which does not have a device formed in the cell so that the route through may be taken. Connection is then made to the first metallization layer in the routing column 28 and then horizontally in the second metallization layer to the second device in the gate cell 24B.
There are a number of disadvantages that arise from the above-described architecture, including the unbalanced rise and fall time of the P and N channel devices which are of the same size. Changing the relative sizes of the P diffusion area and the N diffusion area is difficult due to the limitations created by the cell routing. Also, higher densities are difficult to achieve due to the practice of providing unvarying track pitches between the routing tracks, both in the vertical and in horizontal directions, in order to meet the minimum design standards. In addition, due to the low porosity, power buses typically only have one contact with the individual devices, so that there is a relatively high effective resistance and relatively unreliable contact since it is only being made at one point.
A further consideration of gate array design is the size of the gate cell, which is typically 8 transistors, as seen in prior art FIG. 1. This cell size is due in part to the well taps 16 and 18 that are located between the devices. A reduction in cell size would have a number of advantages for a designer, including tighter placement, reduced dead space within cells, and more flexibility in location of gaps in the cell placement for global routing.